Semiconductor memory device
US9780170B2 · kind B2 · utility
15Cited by
0References
23Claims
0Family size
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Key dates
| Filing date | Jul 7, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Jul 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.