Insulated gate type semiconductor device having floating regions at bottom of trenches in cell region and circumferential region and manufacturing method thereof
US9780205B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 4, 2014 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Aug 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.