Semiconductor structure and manufacturing method thereof
US9780251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2017 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Mar 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/11
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.