Fault isolation system and method for detecting faults in a circuit
US9784788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Nov 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and a fault isolation system for detecting errors in an integrated circuit. One feature of the present invention is using a movable second probe to scan and acquire an output signal through the vias or metal line structure of a diagnostic area along a detecting line, so as to find the fault location precisely, and another feature of the present invention is using a cutter in conjunction with the above method to narrow down the fault range. The cutter is used to electrically isolate the portion of diagnostic area step by step for approaching the fault location. This method can help to save a lot of analysis time and also makes the minor fault localization possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.