Method for testing through silicon vias in 3D integrated circuits
US9784790B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Dec 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2879
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A design-for-test (DFT) architecture for testing a three dimensional (3D) integrated circuit, may comprise a two dimensional (2D) silicon layer n−1 and a 2D silicon layer n connected together with a through silicon via (TSV) having a first side and a second side; scannable latch circuits on said first side and said second side of said TSV, wherein said scannable latch circuits: control flow of data between said layer n−1 and said layer n and allow said TSV to be verified; allow launch and capture clocks to be applied with variable delay in order to perform an alternating current delay fault test between said layer n−1 and said layer n; and have a quiescent state supply current (IDDq) test function built in which allows selection of an input load for a unidirectional signal connection between said layer n−1 and said layer n.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.