Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
US9785423B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 23, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Apr 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30003
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.