Three source operand floating-point addition instruction with operand negation bits and intermediate and final result rounding
US9785433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Mar 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30185
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a decode unit to decode a three source floating point addition instruction indicating a first source operand having a first floating point data element, a second source operand having a second floating point data element, and a third source operand having a third floating point data element. An execution unit is coupled with the decode unit. The execution unit, in response to the instruction, stores a result in a destination operand indicated by the instruction. The result includes a result floating point data element that includes a first floating point rounded sum. The first floating point rounded sum represents an additive combination of a second floating point rounded sum and the third floating point data element. The second floating point rounded sum represents an additive combination of the first floating point data element and the second floating point data element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.