Methods and systems for memory de-duplication
US9785571B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 7, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Nov 3, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are methods and systems for de-duplicating cache lines in physical memory by detecting cache line data patterns and building a link-list between multiple physical addresses and their common data value. In this manner, the methods and systems are applied to achieve de-duplication of an on-chip cache. A cache line filter includes one table that defines the most commonly duplicated content patterns and a second table that saves pattern numbers from the first table and the physical address for she duplicated cache line. Since a cache line duplicate can be detected during a write operation, each write can involve table lookup and comparison. If there is a hit in the table, only the address is saved instead of the entire data string.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.