Verification low power collateral generation
US9785732B2 · kind B2 · utility
3Cited by
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14Claims
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Key dates
| Filing date | Jun 12, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Jun 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a System on Chip (SoC) and/or a Network on Chip (NoC). Such transition state specifications can enable verification of switching behavior when elements/components of a SoC/NoC or a subset thereof switch from one power profile to another, or when the elements/components switch in stable states of power based on inputs such as voltages, clocks, power domains, and traffic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.