Reconfigurable clocking architecture
US9786353B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Feb 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.