Programmable decoupling capacitance of configurable logic circuitry and method of operating same
US9786361B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Jul 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising at least one logic tile including a plurality of multiplexers interconnected into a network configuration, wherein each multiplexer includes a plurality of inputs, an output and a plurality of selection inputs to receive selection signals to determine whether an input of the plurality of inputs is connected to the output. The logic tile further includes (i) at least one inactive multiplexer having an output that is inactive in the network configuration and/or (ii) at least one static multiplexer receiving static selection signals, wherein during operation of the integrated circuit, the selection inputs of the inactive and/or the static multiplexer receive selection signals responsively connect (whether directly or indirectly) two or more inputs of the inactive and/or the static multiplexer to the output of the inactive multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.