Etch damage and ESL free dual damascene metal interconnect
US9786549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Mar 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.