Semiconductor structure and manufacturing method thereof
US9786618B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Nov 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a die including a die pad disposed over the die; a conductive member disposed over and electrically connected with the die pad; a molding surrounding the die and the conductive member; and a redistribution layer (RDL) disposed over the molding, the conductive member and the die, and including a dielectric layer and an interconnect structure, wherein the interconnect structure includes a land portion and a plurality of via portions, the land portion is disposed over the dielectric layer, the plurality of via portions are protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.