Vertical memory devices and methods of manufacturing the same
US9786676B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Jul 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.