Apparatuses having a ferroelectric field-effect transistor memory array and related method
US9786684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Dec 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/2257
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.