Integrated circuit device having an interfacial layer and method of manufacturing the same
US9786761B2 · kind B2 · utility
2Cited by
17References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Dec 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated circuit device includes a substrate including an active region, an interfacial layer including a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16, a gate insulation layer on the interfacial layer, and a gate electrode on the gate insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.