Low-power partial-parallel chien search architecture with polynomial degree reduction
US9787327B2 · kind B2 · utility
3Cited by
8References
24Claims
0Family size
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Key dates
| Filing date | May 7, 2015 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Dec 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.