High order hybrid phase locked loop with digital scheme for jitter suppression
US9787466B2 · kind B2 · utility
4Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Mar 9, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Mar 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.