Super multiply add (super MADD) instructions with three scalar terms
US9792115B2 · kind B2 · utility
1Cited by
5References
21Claims
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Key dates
| Filing date | Dec 23, 2011 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Jun 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.