Three dimensional resistive memory architectures
US9792980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2013 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Oct 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.