Resistive random access memory device
US9792987B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Jul 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture comprises a first memory macro comprising a first plurality of memory cells, a second memory macro comprising a second plurality of memory cells, and a control logic coupled to the first and second memory macros. The control logic is configured to write a logical state to each of the first and second pluralities of memory cells by using first and second signal levels, respectively, thereby causing the first and second memory macros to be used in first and second applications, respectively, the first and second signal levels being different and the first and second applications being different. The first and second memory macros are formed on a single chip, and wherein the first and second pluralities of the memory cells comprise a variable resistance dielectric layer formed using a single process recipe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.