Test structure for monitoring liner oxidation
US9793185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2014 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Oct 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/47
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.