Package-on-package type semiconductor device which is realized through applying not a TSV technology but a fan-out wafer level package technology
US9793217B2 · kind B2 · utility
6Cited by
0References
13Claims
0Family size
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Key dates
| Filing date | Jul 27, 2015 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Aug 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/207
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include a bottom package embedded with a first semiconductor chip. The semiconductor device may include a middle package stacked over the bottom package, and embedded with at least two second semiconductor chips in a fan-out structure. The semiconductor device may include a top package stacked over the middle package, and embedded with at least two third semiconductor chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.