Semiconductor structure and method of forming
US9793230B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Jul 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.