Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction and semiconductor device having reduced junction leakage
US9793272B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 1, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Jun 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.