Ferroelectric gate dielectric with scaled interfacial layer for steep sub-threshold slope field-effect transistor
US9793397B1 · kind B1 · utility
18Cited by
3References
16Claims
0Family size
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Key dates
| Filing date | Sep 23, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Sep 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
A method is presented for forming a semiconductor device. The method includes forming an oxygen containing interfacial layer on a semiconductor substrate, forming a hafnium oxide layer on the interfacial layer, the hafnium oxide layer crystallizing to a non-centrosymmetric phase in a final structure, forming a first electrode containing a scavenging metal, which reduces a thickness of the interfacial layer via an oxygen scavenging reaction in the final structure, on the hafnium oxide layer, and forming a second electrode on the first electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.