Controller, semiconductor memory system and operating method thereof
US9798614B2 · kind B2 · utility
4Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 4, 2015 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Dec 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2957
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An operating method of a controller includes generating error reliability of data based on reliability information of one or more error-corrected bits of the data, wherein the data is read out from a semiconductor memory device and a hard decision ECC decoding to the data through a BCH code is determined as successful; and determining miscorrection of the data based on the error reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.