Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon the mode
US9798668B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2014 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Jun 12, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory stores 2^J-byte cache lines and includes an array of 2^N sets each holding tags each X bits, an input receives a Q-bit memory address, MA[(Q−1):0], having: a tag MA[(Q−1):(Q−X)] and an index MA[(Q−X−1):J]. Q is an integer at least (N+J+X−1). In a first mode: set selection logic selects one set using the index and LSB of the tag; comparison logic compares all but LSB of the tag with all but LSB of each tag in the selected set and indicates a hit if a match; otherwise allocation logic allocates into the selected set. In a second mode: the set selection logic selects two sets using the index; the comparison logic compares the tag with each tag in the selected two sets and indicates a hit if a match; and otherwise allocates into one set of the two selected sets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.