Dram circuit, redundant refresh circuit and refresh method
US9799391B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 2016 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Nov 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM circuit includes an array having a normal word line, a first redundant word line and a second redundant word line immediately adjacent to the first redundant word line. The second redundant word line is activated if the normal word line is assigned, by a memory controller external to the DRAM circuit, to be activated. A redundant refresh circuit is configured to determine that the first redundant word line is required to be refreshed in response to the second redundant word line being activated; and a row decoder is configured to, according to the determination of the redundant refresh circuit, refresh the first redundant word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.