Three dimensional NAND device containing dielectric pillars for a buried source line and method of making thereof
US9799670B2 · kind B2 · utility
41Cited by
17References
25Claims
0Family size
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Key dates
| Filing date | Feb 8, 2016 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Feb 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film, and an array of dielectric pillars located between the alternating stack and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.