Error correction and decoding
US9800271B2 · kind B2 · utility
3Cited by
18References
27Claims
0Family size
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Key dates
| Filing date | Sep 14, 2015 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Dec 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.