Clock phase alignment in data transmission
US9800400B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 2015 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Nov 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method are described for calibrating a clock used in data transmission. In one example, dynamic phase adjustment circuitry can be used for any of a variety of different protocols to shift the clock phase with respect to a data signal. In the most typical example, the clock phase is shifted 90 degrees relative to a transmission data signal. The dynamic phase adjustment circuitry can use two cascaded programmable delay lines coupled in series. Each programmable delay line represents a half phase delay of 90 degrees. A controller can monitor an output of the programmable delay lines and incrementally add or subtract programmable delay line elements until a 180 degree phase is detected relative to a data transmission. An output clock can then be used by applying the result of the calibration delay element to the clock under discussion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.