Partial bad block detection and re-use using EPWR for block based architectures
US9804922B2 · kind B2 · utility
4Cited by
2References
19Claims
0Family size
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Key dates
| Filing date | Jul 21, 2014 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Oct 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for partial bad block reuse may be provided. Data may be copied from a block of a first memory to a block of a second memory. A post write read error may be detected in a first portion the data copied to the block of the second memory without detection of a post write read error in a second portion of the data copied to the block of the second memory. The block of the second memory may be determined to be a partial bad block usable for storage in response to detection of the post write read error in the first portion of the data but not in the second portion of the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.