Memory mirroring utilizing single write operations
US9804931B2 · kind B2 · utility
1Cited by
7References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 12, 2014 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Jun 2, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.