Automated stressing and testing of semiconductor memory cells

US9805823B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Yuen H. Chan · Poughkeepsie, US
• Michael Kugel · Eppelheim, DE
• Stefan Payer · Stuttgart, DE
• Wolfgang Penth · Holzgerlingen, DE
• Juergen Pille · Stuttgart, DE
• Tobias Werner · Holzgerlingen, DE

Key dates

• Filing date: Jan 25, 2017
• Grant date: Oct 31, 2017
• Expiry date: Jan 25, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/1204
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory cell readable through a bit line and addressable through a word line can be stressed by applying a stress voltage to the bit line for a stress voltage time, and addressing the memory cell through the word line for an addressing time included within the stress voltage time. The memory cell can be tested by writing a data value into the memory cell, stressing the memory cell, reading the stored value from the memory cell, and determining whether the stored value corresponds to the data value. A testable memory array can include a memory cell addressable through a word line and readable through a bit line, a precharge circuit, a stress circuit, and an array built-in self test (ABIST) circuit. The ABIST circuit can be configured to stress the memory cell by applying a stress signal to the stress circuit.