Method and apparatus for testing integrated circuit
US9805826B2 · kind B2 · utility
3Cited by
16References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2015 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Feb 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. Flip-flops of the IC are connected together into at least one serial scan chain. The test interface unit receives test data including MBIST configuration data. The MBIST unit, in a first mode, tests the memory based on the MBIST configuration data at least partly in parallel with a scan test using the scan chain. Thus, both the memory and the logic circuitry can be tested in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.