Reinforced wafer level package comprising a core layer for reducing stress in a solder joint and improving solder joint reliability

US9806063B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Chin-Kwan Kim · San Diego, US
• Rajneesh Kumar · Poughkeepsie, US
• Vladimir Noveski · San Diego, US
• Jie Fu · Beijing, CN
• Ahmer Syed · Chandler, US
• Milind Shah · San Diego, US
• Omar J. Bchir · Phoenix, US

Key dates

• Filing date: Apr 29, 2015
• Grant date: Oct 31, 2017
• Expiry date: Apr 29, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.