Integrated circuit devices having a Fin-type active region and methods of manufacturing the same
US9806075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Jan 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.