Non-uniform spacing in transistor stacks
US9806094B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Aug 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
Field effect transistor stacks include a first field-effect transistor having a source finger, a drain finger, and a gate finger interposed therebetween, the source finger and the drain finger of the first field-effect transistor being separated by a first drain-to-source distance, and a second field-effect transistor in a series connection with the first field-effect transistor, the second field-effect transistor having a source finger, a drain finger, and a gate finger interposed therebetween, the source finger and the drain finger of the second field-effect transistor being separated by a second drain-to-source distance that is different than the first drain-to-source distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.