Metal configurable register file
US9811628B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Oct 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to a configurable register file for inclusion in ASIC and other integrated circuit designs such as those based on metal configurable standard cell (MCSC) technology. According to certain general aspects, configurable register files provided by the present embodiments improve area, power and routing efficiencies and flexibility over conventional approaches such as hard memory macros and RTL designs. In embodiments, a configurable register file is implemented as a soft macro constructed from metal configurable standard cell (MCSC) base cells. According to certain aspects, unlike a hard memory macro, width and depth are not fixed and can be configured or programmed to any desired dimension or configuration. In some embodiments, a bit array of a configurable register file is comprised of register file bit cells. In other embodiments, a bit array of a configurable register file is comprised of ROM bit cells. In these and other embodiments, a configurable register file is constructed with a bit-line sharing approach that improves the routing and logic resource usage as compared to RTL based memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.