DRAM adjacent row disturb mitigation
US9812185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Feb 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention pertains to data disturb vulnerabilities in Dynamic Random Access Memory (DRAM) integrated circuits. In particular, it pertains to mitigating attacks on a computational system by deliberate inducement of disturbs on a targeted row (also known as “row hammering”) in the system's DRAM memory. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate. When a tracked address poses a danger of causing a memory disturb, each row adjacent to the tracked address row is refreshed thus mitigating the danger.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.