MTJ-based content addressable memory with measured resistance across matchlines
US9812205B2 · kind B2 · utility
4Cited by
2References
20Claims
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Key dates
| Filing date | Jul 8, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Jul 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the subject invention provide a three transistor, two domain-wall-based magnetic tunnel junction CAM cell (3T-2DW-MTJ CAM). A four transistor, two magnetic tunnel junction ternary CAM cell (4T-2MTJ TCAM) is also provided. An array of the provided CAM cells forms words of various lengths, such as 4-bit, 8-bit, and 16-bit words. Longer CAM words can be formed by an array having hierarchical structures of CAM cells having smaller word sizes, such as 4-bit words or 8-bit words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.