Method and apparatus for in-system management and repair of semi-conductor memory failure
US9812222B2 · kind B2 · utility
4Cited by
7References
30Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 20, 2015 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Sep 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.