Integrated circuit package pad and methods of forming
US9812337B2 · kind B2 · utility
57Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2015 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Jun 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.