Interconnect structures for assembly of multi-layer semiconductor devices
US9812429B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2015 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Nov 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-layer semiconductor device includes a first semiconductor structure having first and second opposing surfaces, the second surface of the first semiconductor structure having at least a first semiconductor package pitch. The multi-layer semiconductor device also includes a second semiconductor structure having first and second opposing surfaces, the first surface of the second semiconductor structure having a second semiconductor package pitch. The multi-layer semiconductor device additionally includes a third semiconductor structure having first and second opposing surfaces, the first surface of the third semiconductor structure having a third semiconductor package pitch which is different from at least the second semiconductor package pitch. The second and third semiconductor structures are provided on a same package level of the multi-layer semiconductor device. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.