Methods and systems for reducing electrical disturb effects between thyristor memory cells using buried metal cathode lines
US9812454B2 · kind B2 · utility
5Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Jun 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/676
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.