Bottom-gate thin-body transistors for stacked wafer integrated circuits
US9812555B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2015 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Dec 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/199
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having a thickness that is defined by shallow trench isolation structures that provide complete well isolation for the transistors. The transistors may include gate terminal contacts formed through the shallow trench isolation structures, bulk terminal contacts that are formed through the thinned substrate and that overlap with the gate contacts, and source-drain terminal contacts with in-situ salicide. Additional metallization layers may be formed over the gate/bulk/source-drain contacts after bonding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.