Test probing structure
US9817029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2011 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | May 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16225
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.