Parallel concurrent test system and method
US9817062B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 23, 2017 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Jan 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2893
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.