Method and apparatus for determining feasibility of memory operating condition change using different back bias voltages
US9817601B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2016 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Jul 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having at least one output predicting a feasibility of whether the memory device will work properly at a different operating condition including a different supply voltage and/or a different operating frequency than the current supply voltage and/or the current operating frequency. A semiconductor device (e.g. a SoC chip) provides a test to either validate or invalidate the feasibility for the memory device to enter such a different operating condition based on read and write operations of the memory device in normal access cycles. The memory device is partitioned with at least a first memory unit and a second memory unit, which can be coupled to different back-bias voltages. This operating condition predicting function can be enabled or disabled by the semiconductor device in real time operation depending on the feasibility test results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.